1. Field of the Invention
This invention relates generally to integrated circuits, and in particular to an improved apparatus and method for increasing comparator gain of a switchover circuit of an integrated circuit device without affecting standby current.
2. Background of the Invention
There are many environments today in which it is desirable to retain data in integrated circuits in the event that the primary, and typically external, power supply provided to an integrated circuit is interrupted or lost. In memory devices, for example, commercially available circuitry retains data in static random access memories (SRAMs) when primary power is removed. Representative examples of these devices, often referred to as "zero power circuits or devices," are described in the following patents: U.S. Pat. No. 4,122,359, entitled Memory Protection Arrangement; U.S. Pat. No. 4,451,742, entitled Power Supply Control for Integrated Circuit; U.S. Pat. No. 4,713,555, entitled Battery Charging Protection Circuit; and U.S. Pat. No. 5,099,453, entitled Configuration Memory for Programmable Logic Device. In a zero power circuit, the contents of the circuit are typically protected in the event that the primary power supply voltage to the circuit drops below a predetermined or selected voltage level that is normally defined to be a secondary or back-up voltage, such as a voltage supplied from a battery power supply.
In order to switch from the primary power supply to the secondary power supply upon failure of the primary power supply, typically the voltage level of both the primary and secondary power supplies be monitored and compared relative to each other. Comparators are particularly suited to this purpose. Comparator circuitry will sense when the primary power supply voltage provided to the circuit drops below the secondary power supply voltage by comparing these two voltages and the zero power circuit will accordingly cause the integrated circuit to receive power from the secondary power supply rather than from the primary power supply. The comparator circuitry also senses when the primary power source becomes larger than the secondary, battery power source so that the zero power circuit will want to switch from the secondary power supply back to the primary power supply voltage. Such is the case when the primary power supply is turned on and is ramping up to its nominal voltage level. The secondary, battery back-up power supply will need to supply the integrated circuit until the primary power supply has exceeded the secondary power supply.
A difficulty in comparing the primary power supply to the secondary power supply in order to determine how the integrated circuit device should be powered is the relative instability of the battery supply source itself. It is not uncommon for batteries to vary from approximately 2.9 volts to 3.4 volts, for instance, for a 3.3 volt integrated circuit device. Given the possible wide range of battery voltage, it is considered advantageous to determine which of the primary or secondary power sources should power the integrated circuit device based upon the voltage level of the more stable external, primary power supply. For this reason, it is often better to compare the external primary power supply voltage to a defined voltage in order to determine whether the integrated circuit device will be powered by the primary power source or the secondary power source.
Referring now to FIG. 1, a system 10 for switching between a primary power supply and a secondary power supply to power an integrated circuit device, according to the prior art, is illustrated. System 10 contains a switchover circuit that operates to switch between a two power sources capable of powering a 3.3 volt integrated circuit device, such as a Zeropower.RTM. or Timekeeper.RTM. memory device, capable of being powered by an external, primary power supply Vcc1 or an on-chip battery voltage source 42. Vcc1 is a voltage provided to the integrated circuit device by an external primary power supply source external to the integrated circuit and battery 42 is a secondary or back-up power supply source typically resident on-chip the integrated circuit device. System 10 of the integrated circuit device determines whether Vcc1 or battery voltage will power the integrated circuit device as a function of the magnitude of Vcc1 in comparison to a defined switchover point-in this example, 2.7 volts for a 3.3 volt integrated circuit device.
The system 10 is comprised of a switchover circuit, primary and secondary power supplies. The switchover circuit is comprised of a number of circuit elements, including PMOS transistors 12, 18, 20, and 32, NMOS transistors 14, 16, 22, 30, and 34, and comparator 28 and is provided with or coupled to Vref reference voltage 24, voltage signal 26, Vcc1, ground voltage Vss, and battery voltage 38 produced by battery 42. The output node 36 of the switchover circuit will typically be provided to the substrate or switch Vcc of the integrated circuit device. Q1 transistor 12 has a width to length ratio of 5/20 and transistor 14 has a width to length ratio of 5/10. A first source/drain of Q1 transistor 12 is coupled to Vcc1, a second source/drain of Q1 transistor 12 is coupled to a first source/drain and gate terminal of transistor 14, and a gate of Q1 transistor 12 is coupled to ground or Vss voltage potential. A second source/drain of transistor 14 is coupled to Vss potential. A first source/drain of transistor 18, a first source/drain of transistor 20 and a first source/drain of transistor 32 are likewise coupled to Vcc1 potential. A second source/drain of transistor 16, a second source/drain of transistor 22, and a second source/drain of transistor 30 are coupled to Vss potential. A second source/drain of transistor 18 is coupled to the gate terminal of transistor 18, the gate terminal of transistor 20, and a first source/drain of transistor 16, as shown. A second source/drain of transistor 20 is coupled to the first source/drain and the gate terminal of transistor 22. A first source/drain of transistor 30 is a control input to comparator 28. The Vso signal output 29 of comparator 28 is coupled to the gate terminal of transistor 32 and the gate terminal of transistor 34. A second source/drain of transistor 32 and the positive voltage terminal 38 of battery 42 together form an output node 36 of system 10 that is provided to the substrate or switch Vcc of the integrated circuit device.
The substrate of each of the PMOS transistors 12, 18, 20, and 32 are coupled to the switch Vcc. When external power supply Vcc1 is off (0 volts), the integrated circuit device is powered up by battery 42, with the substrate of PMOS transistors 12, 18, 20, and 32 at the battery voltage level 38 produced by battery 42. The voltage 38 supplied by battery 42 can typically vary from approximately 2.9 volts to 3.4 volts, depending upon the particular battery 42. Thus, when the integrated circuit device is powered up by battery 42, the substrates of PMOS transistors 12, 18, 20, and 32 can be biased at the battery voltage 38 of approximately 2.9 volts or higher.
Vref 24 and signal 26 are generated based on the Vcc1 level and compared by comparator 28. Vref signal 24 tracks Vcc1 voltage and is generally approximately 1.25 volts less than Vcc1 for a 3.3 volt device. Voltage signal 26 also tracks Vcc1 but at a slower rate. Vref signal 24 and signal 26 cross when Vcc1 is approximately 2.7 volts, the defined crossover point, regardless of the voltage 38 generated by battery 42. When Vcc1 is below 2.7 volts, Vref signal 24 is less than voltage signal 26 and Vso comparator output signal 29 transitions from a low to a high logic state to cause the integrated circuit device to be powered up by battery 42. When, however, Vcc1 is above 2.7 volts, Vref signal 24 is greater than signal 26 and thus Vso signal 29 transitions from a high to a low logic state and the device is powered up by externally provided voltage Vcc1. Given the wide range of possible battery voltages 38 supplies by battery 42, from approximately 2.9 to approximately 3.4 volts, the comparison of Vref signal 24 and voltage signal 26 by comparator 28 ensures that switchover between primary and secondary power sources is dictated by the relatively stable external power supply Vcc1 and not the battery voltage 38; Vso comparator output signal 29 will transition low or high solely as a function of Vcc1 and not battery voltage 38.
A problem with FIG. 1 arises as external power supply Vcc1 is ramping up and battery 42 is powering the integrated circuit device. Since all of the PMOS transistor substrates are on the switch Vcc of the integrated circuit when the integrated circuit device is powered up by the battery 42, the substrates of the PMOS transistors are at the battery voltage of 2.9 volts or higher. Q1 transistor 12 is in the back bias mode with its substrate at the battery voltage level as Vcc1 is ramping up and the device is powered by the battery 42. When Q1 transistor is thus back biased, the current through Q1 transistor 12 is mirrored at different gains to comparator 28 through the mirror legs formed by transistors 16, 18 and 20, 22 since Q1 transistor 12 in its back-biased mode does not generate enough current to cause the comparator to operate in a stable condition.
At the crossover point of 2.7 volts, the integrated circuit device will switch to the external supply Vcc1. If at this time the battery voltage 38 of battery 42 is 3 volts, for instance, then the substrate of PMOS transistors is also 3 volts and Q1 transistor 12 is back-biased, causing the current through node N1 to be less than that required by comparator 28 to operate in a stable manner. Comparator 28 stabilizes when the substrate of the integrated circuit device is driven down to the Vcc1 level, from 3 volts to 2.7 volts in this case, so that the PMOS transistors 12, 18, 20, and 32 are no longer back-biased. If the substrate is estimated to have 500 pF of capacitance, it can be expected to take approximately 8 to 10 nS to be driven down to the Vcc1 voltage level and approximately another 50 nS to stabilize and level off. As a result, comparator output signal 29 oscillates between a high logic state in which the battery will attempt to power the device and a low logic state in which the external power supply Vcc1 will attempt to power the device and the battery current will discharge-all because the current source through node N1 is not sufficient to cause comparator 28 to operate in a stable condition. When Vso comparator output signal 29 bounces from a low to a high state due to this unstable condition, current is unnecessarily drawn from battery 42 thereby shortening the operating life of the battery, particularly in environments in which a switchover between primary and secondary power sources occurs with some regularity. An example of this type of oscillation of signal 29 is shown in FIG. 2.
The instability of the comparator may cause the comparator circuitry output signal to "bounce" before it can settle to the proper level. A temporary, improper comparator circuitry output signal can cause the integrated circuit to be powered by the secondary, battery power supply even when the primary power source is higher than the defined crossover voltage point. Switching back to the battery while the primary power supply is higher than the battery level will cause an unnecessary high dynamic current to be drawn from the battery that will have the unfortunate consequence of reducing the battery life, particularly in those applications in which the external, principal power supply is switched on and off with some frequency.
From the foregoing description, it can be seen that there is a need in the art to ensure that the comparator be stabilized so that the output signal of the comparator circuitry be immediately reflective of its true logic state, in order to prevent false switching between the primary and secondary power supplies. Addressing this problem of the prior art will provide a more stable switchover between primary and second power supplies as well as prolong the life of the internal secondary, battery back-up power supply of the integrated circuit.